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Chapter 1 Overview and Configuration

 
The function of the General Purpose Input Output (GPIO) interface is to provide a means of communication between a peripheral device and a computer.
 
Block Diagram of the GPIO Interface
 
The GPIO interface uses a 50 pin connector to communicate with the peripheral. Thirty-two lines are used for data input and output; sixteen for output (DO0 - DO15) and sixteen for input (DI0 - DI15).
 
 
GPIO 650 Hardware Setup
The GPIO 650 board has three switches that are used to configure the board. An understanding of the GPIO interface is necessary to properly set the switches. If you have not previously used the GPIO interface please study the Interface Description section before proceeding with the installation.
Switches labeled RES are reserved and currently unused. The switch is ON when it is toward the PC board and OFF when it is away from the board.
 
 
Location of Switches for the GPIO 650
 
  GPIO 650 Switch 1
 
GPIO 650 Switch One - Interface Settings
This switch selects the signal polarity, type of handshaking and the state of the output data lines after reset. The table shows the effect of each switch setting.
Interface Settings for GPIO 650
Name of Switch Position
PCTL
PFLG
PSTS
HND
DIN
DOUT
DCLR
Function
Set
Polarity of PCTL
Set
Polarity of PFLG
Set
Polarity of PSTS
Full/Pulse
Handshake
Set
Polarity of Data In
Set
Polarity of Data Out
Clear DOUT on Reset
ON
Low = Set
High = Clr
Low = Rdy
High = Bsy
Low = OK
High = OK
Full
Low = 1
High = 0
Low = 1
High = 0
Yes
OFF
Low = Clr
High = Set
Low = Bsy
High = Rdy
Low = OK
High = OK
Pulse
Low = 0
High = 1
Low = 0
High = 1
No
 
  GPIO 650 Switch 2
 
GPIO 650 Switch Two - Input Clock Source
Switch two selects the latch source that will clock the data into the input data buffers. The switch for the desired clock should be off with the other two on. The clocks for the high and low bytes do not need to be the same.
 
The RD clock source causes the computer to clock the input buffers whenever it is reading the data. The BSY clock source causes the input buffers to be loaded on the ready-to-busy transition of PFLG. The RDY clock source uses the busy-to-ready transition of PFLG.
 
By default these settings select the input clock source. Software can override these settings. If only software control is used for the input clock source selection this switch does not need to be set.
 
For more information on GPIO input clocking, refer to the Interface Description section for a more detailed explanation.
 
  GPIO 650 Switch 3
 
GPIO 650 Switch Three - I/O Address
This switch is used to select the I/O address of the board. The I/O address is the base address that the computer uses to communicate with the board. The GPIO 650 board uses 8 address locations above and including the base address. The address space of the GPIO board cannot be shared with any other peripheral. The default address of the GPIO board is 380h.
 
The following table shows the switch settings with the corresponding hexadecimal board address.
 
Address Selection for GPIO 650
Switches
I/O Address
Switches
I/O Address
A9         A3
(hex)
A9          A3
(hex)
1 0 0 0 0 0 0
0 0
1 0 0 0 0 0
0 0
1 0 0 0 0 0 1
0 8
1 0 0 0 0 1
0 8
1 0 0 0 0 1 0
1 0
1 0 0 0 1 0
1 0
1 0 0 0 0 1 1
1 8
1 0 0 0 1 1
1 8
1 0 0 0 1 0 0
2 0
1 0 0 1 0 0
2 0
1 0 0 0 1 0 1
2 8
1 0 0 1 0 1
2 8
1 0 0 0 1 1 0
3 0
1 0 0 1 1 0
3 0
1 0 0 0 1 1 1
3 8
1 0 0 1 1 1
3 8
1 0 0 1 0 0 0
4 0
1 0 1 0 0 0
4 0
1 0 0 1 0 0 1
4 8
1 0 1 0 0 1
4 8
1 0 0 1 0 1 0
5 0
1 0 1 0 1 0
5 0
1 0 0 1 0 1 1
5 8
1 0 1 0 1 1
5 8
1 0 0 1 1 0 0
6 0
1 0 1 1 0 0
6 0
1 0 0 1 1 0 1
6 8
1 0 1 1 0 1
6 8
1 0 0 1 1 1 0
7 0
1 0 1 1 1 0
7 0
1 0 0 1 1 1 1
7 8
1 0 1 1 1 1
7 8
1 0 1 0 0 0 0
8 0
1 1 0 0 0 0
8 0
1 0 1 0 0 0 1
8 8
1 1 0 0 0 1
8 8
1 0 1 0 0 1 0
9 0
1 1 0 0 1 0
9 0
1 0 1 0 0 1 1
9 8
1 1 0 0 1 1
9 8
1 0 1 0 1 0 0
A 0
1 1 0 1 0 0
A 0
1 0 1 0 1 0 1
A 8
1 1 0 1 0 1
A 8
1 0 1 0 1 1 0
B 0
1 1 0 1 1 0
B 0
1 0 1 0 1 1 1
B 8
1 1 0 1 1 1
B 8
1 0 1 1 0 0 0
C 0
1 1 1 0 0 0
C 0
1 0 1 1 0 0 1
C 8
1 1 1 0 0 1
C 8
1 0 1 1 0 1 0
D 0
1 1 1 0 1 0
D 0
1 0 1 1 0 1 1
D 8
1 1 1 0 1 1
D 8
1 0 1 1 1 0 0
E 0
1 1 1 1 0 0
E 0
1 0 1 1 1 0 1
E 8
1 1 1 1 0 1
E 8
1 0 1 1 1 1 0
F 0
1 1 1 1 1 0
F 0
1 0 1 1 1 1 1
F 8
1 1 1 1 1 1
F 8
 
GPIO 650 Interrupt and DMA Channels
Interrupts and DMA are used to assist the transferring of data. There are a fixed number of interrupt and DMA channels on a PC and they cannot be shared with other devices. The GPIO 650 enables the channel(s) for use with software so no hardware settings are required.
 
Interrupt Channels     5, 7, 9, 10, 11, 12, 15
 
DMA Channels    5, 6, 7
 
The board can use one interrupt channel and one DMA channel. An interrupt must be selected for DMA to be used. These channels numbers are given to the software driver during the initialization procedure. If there are no interrupt or DMA channels allocated to the board it can still be used to transfer data but it’s performance will decrease and interrupts will not be available.
 
The three DMA channels are the 16-bit DMA channels available on a PC. These channels do not support 8-bit transfers. To handle this limitation the GPIO 650 was designed to pack two 8-bit peripheral handshakes into a single DMA transfer. This not only allows 8-bit peripheral transfers but also doubles the effective 8-bit transfer rate of the GPIO board.
More detailed information on DMA transfers is in Interface Description under DMA Transfers.
 
GPIO 600 Hardware Setup
The GPIO 600 board has three switches that are set to configure the board. An understanding of the GPIO interface is necessary to properly set the switches. If you have not previously used the GPIO interface please study the Interface Description section before proceeding with the installation.
 
Switches labeled RES are reserved. The switch is ON when it is toward the PC board and OFF when it is away from the board.
 
Location of Switches and Jumpers on the GPIO 600
 
GPIO 600 Switch 1
 
GPIO 600 Switch One - I/O Address
This switch is used to select the I/O address of the board. The I/O address selected by this switch is the base address that the computer uses to communicate with the board. The GPIO board uses 16 address locations above the base address. The address space of the GPIO board cannot be used by any other peripheral. The default address of the GPIO board is 380h.
 
The following table shows the switch settings with the corresponding hexadecimal board address.
 
Address Selection for GPIO 600
Switches
I/O Address
A10         A4
(hex)
0 1 0 0 0 0 0
2 0 0
0 1 0 0 0 0 1
2 1 0
0 1 0 0 0 1 0
2 2 0
0 1 0 0 0 1 1
2 3 0
0 1 0 0 1 0 0
2 4 0
0 1 0 0 1 0 1
2 5 0
0 1 0 0 1 1 0
2 6 0
0 1 0 0 1 1 1
2 7 0
0 1 0 1 0 0 0
2 8 0
0 1 0 1 0 0 1
2 9 0
0 1 0 1 0 1 0
2 A 0
0 1 0 1 0 1 1
2 B 0
0 1 0 1 1 0 0
2 C 0
0 1 0 1 1 0 1
2 D 0
0 1 0 1 1 1 0
2 E 0
0 1 0 1 1 1 1
2 F 0
0 1 1 0 0 0 0
3 0 0
0 1 1 0 0 0 1
3 1 0
0 1 1 0 0 1 0
3 2 0
0 1 1 0 0 1 1
3 3 0
0 1 1 0 1 0 0
3 4 0
0 1 1 0 1 0 1
3 5 0
0 1 1 0 1 1 0
3 6 0
0 1 1 0 1 1 1
3 7 0
0 1 1 1 0 0 0
3 8 0
0 1 1 1 0 0 1
3 9 0
0 1 1 1 0 1 0
3 A 0
0 1 1 1 0 1 1
3 B 0
0 1 1 1 1 0 0
3 C 0
0 1 1 1 1 0 1
3 D 0
0 1 1 1 1 1 0
3 E 0
0 1 1 1 1 1 1
3 F 0
 
  GPIO 600 Switch 2
 
GPIO 600 Switch Two - Interface Settings
 
This switch selects the signal polarity and the type of handshaking that will be used. The chart below shows the switch settings for handshaking and polarity.
 
Interface settings for GPIO 600
Name of Switch Position
PCTL
PFLG
PSTS
HND
DIN
DOUT
RES
Function
Set Polarity of PCTL
Set Polarity of PFLG
Set Polarity of PSTS
Full/Pulse Handshake
Set Polarity of Data In
Set Polarity of Data Out
Reserved
ON
Low = Set
High = Clr
Low =  Rdy
Higher = Bsy
Low = OK
Low = OK
Full
Low = 1
High = 0
Low =1
High = 0
 
OFF
Low = Clr
High = Set
Low = Bsy
High = Rdy
Low = OK
High = OK
Pulse
Low = 0
High = 1
Low = 0
High = 1
 
 
  GPIO 600 Switch 3
 
GPIO 600 Switch Three - Input Clock Source
 
This switch selects the latch source that will clock the data into the input data buffers. The switch for the desired clock should be off with the other two on. The clocks for the high and low bytes do not need to be the same.
 
The RD clock source causes the computer to clock the input buffers whenever it is reading the data. The BSY clock source causes the input buffers to be loaded on the ready-to-busy transition of PFLG. The RDY clock source uses the busy-to-ready transition of PFLG.
 
For more information on GPIO input clocking, refer to the Interface Description section for a more detailed explanation.
 
Interrupt Jumper
The GPIO 600 supports interrupts 2 through 7. The default interrupt is 5. The location of the interrupt selector pins can be found on the board diagram at the start of this section. Install the shorting block on the pins that corresponds to the desired interrupt number.
 
DOUT Clear Jumper
If the DOUT Clear jumper is set, the output data lines will be set low after a board reset. The location of the DOUT Clear jumper can be seen on the board diagram at the start of this section.
 
Board Installation
1.   Turn off and unplug the computer
2.   Remove the computer cover.
3.   Locate an empty slot and take off the slot cover by removing the screw. Keep the screw.
4.   Eliminate any static electricity by touching the metal computer case.
5.   Remove the GPIO board from the static protection pouch and insert it into the selected slot. The board should be handled by its edges only.
6.   Replace the screw to hold the board in place.
7.   Replace the computer cover.