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Chapter 2 Interface Description

 
This section describes the operation of the GPIO interface.
 
 
External Connections to GPIO
 
Signal Descriptions
All of the signal lines of the GPIO board are described below. The numbers in parentheses are the pin numbers on the connector.
 
Parallel Data Out
Data Output Lines (2-17) - These are the sixteen data output lines. The computer writes to these lines while the peripheral reads them. The logic sense of these lines is user configurable.
 
Parallel Data In
Data Input Lines (27-42) - These are the sixteen data input lines. The peripheral writes to these lines while the computer reads them. The logic sense of these lines is user configurable.
 
Handshake
Peripheral Control (19) - PCTL - This is the control line that the computer sets to initiate a transfer of data. The logic sense of this line is user configurable.
Input Output (20) - IO - This line indicates the direction of data flow to the peripheral. A high signal indicates an input while a low signal indicates an output.
Peripheral Flag (44) - PFLG - The peripheral uses this line to acknowledge the transfer. The logic sense of this line is user configurable.
 
Special Purpose
Peripheral Status (45) - PSTS - This line can be used to indicate the OK or not OK status of the peripheral. The logic sense of this line is user configurable.
Peripheral Reset (21) - PRESET - This is the reset line. It pulses low for at least 15 microseconds whenever a reset takes place.
External Interrupt Request (46) - EIR - This line allows the peripheral to interrupt the computer. The EIR line is active low.
 
General Purpose
Control 0 and 1 (22,23) - CTL0, CTL1 - These are general-purpose lines that the computer can set.
Status 0 and 1 (47,48) - STI0, STI1 - These are general-purpose lines that the computer can read.
 
Grounds
Grounds (18,24,26,43,49) - GND - These are the signal grounds. These pins provide the ground potential for the signal lines.
Chassis Ground (25) - CHGND - This pin is connected to the IO bracket that screws into the PC chassis. It is usually used to connect to the cable shield.
 
Differences Between GPIO 600 and GPIO 650
The GPIO 600 and 650 are both designed to provide the same interface for communication with digital peripherals. All interaction with the peripheral are essentially the same. The differences come from the interaction between the GPIO board and the host computer. There are also some configuration differences.
 
The GPIO 650 has a 16-bit interface with the host computer and can use DMA to transfer data. The GPIO 600 uses an 8-bit interface and does not support DMA. The wider data path and the available DMA can allow the GPIO 650 to transfer data significantly faster with fast peripherals than the GPIO 600.
 
 
Since the GPIO 650 has a 16-bit interface it has access to the high numbered interrupt sources. These higher sources, greater than 9, are more available than the lower sources making it easier to locate a free interrupt channel.
 
The input clock source is set on both boards with a dip switch but on the GPIO 650 the software can override these settings.
 
The PCTL delay time is modified on the GPIO 600 by soldering in a capacitor or a resistor. The PCTL delay time for the GPIO 650 is selected from software. This limits the maximum delay on the GPIO 650 to 1.5μs while the GPIO 600 can be extended to 100’s of microseconds with the use of a large capacitor.
 
The DOUT clear jumper on the GPIO 600 and switch on the GPIO 650 clears the DOUT lines on reset. With the GPIO 600 this forces the output lines low regardless of the polarity set for the output lines. The GPIO 650 sets the lines to a logical 0. This allows the lines to be set low or left high impedance depending on the polarity set for the lines.
 
Interfacing Circuits
This section gives the electrical requirements for the GPIO interface and some suggestions on interfacing circuits.
 
Peripheral Driver Circuit
All signal and data input lines are connected to a TTL input. The data lines are pulled up to 3.4V with a 3k/6.2kΩ resistor divider. The signal lines are pulled up to 3.4V with a 1.5k/3.1kΩ resistor divider. Input voltages above 5.5V or below -0.5V can result in damage to the GPIO board.
 
Peripheral Drive Requirements:
Iin low           = 2mA — data lines
       = 4.5mA — signal lines (PFLG, PSTS, STI0, STI1)
Vin max         = 5.5V
Vin high         > 2.0V
Vin low           < 0.7V — data lines
         < 0.6V — signal lines
 
Driver Circuit Suggestions
Peripheral Receiving Circuit
 
All of the GPIO outputs, both for signals and data, use open collector output buffers. This means that the line is either left free for a high signal, high impedance, or being pulled to ground for a low signal. This has two effects: first, the computer can write to devices running off any voltage up to 30V, second, the driver must be pulled to the high voltage or the peripheral will probably always read a low.
 
GPIO16 Output Driver Specifications:
Vout low           = 0.4V max while sinking 16mA
         = 0.7V max while sinking 40mA
Vout high           = 30V max
Iout low           = 40mA
 
Receiver Circuit Suggestions
 
Data Settling Times
The data settling time is the time from when the peripheral or the computer writes the data until that data is valid. The length of the cable and the type of driver affects the settling time for a particular application. If sufficient time is not provided for the data to settle erratic data errors will occur.
 
PCTL Delay Time
The PCTL delay time sets the time from when the data is written to the output buffers until the PCTL line is set. The transition of PCTL from clear to set, indicates to the peripheral that the data is valid.
 
On the GPIO 650 the PCTL delay time is set with software from 0-100ns to 1.4-1.5μs. Refer to Chapters 3 or 5 for information on setting the PCTL Delay time.
With the GPIO 600 a resistor is added to shorten the delay time. A capacitor is added to lengthen the delay time. The resistor or capacitor must be soldered onto the board. The locations for R4 and C2 are shown in the board diagram in chapter 1.
 
GPIO 600 Equations for PCTL Delay Time
To decrease time constant:
To increase time constant:
 
Peripheral Delay Time
The peripheral must also insure that the data is has written is stable at the GPIO board before it latches the data into the input buffers. The peripheral should delay its response with PFLG until the data has settled.
 
Data Handshaking
Data handshaking is the process of using signals between the computer and peripheral to inform the other when it is ready to receive or transmit data. This section describes the use of the handshaking lines and demonstrates the data flow that these lines allow.
 
In the following discussion Full and Pulse Mode Handshaking are shown. The selection between Full and Pulse mode is made with the HND switch described in Chapter 1.
For inputs the computer reads the contents of the input data buffers on the GPIO board and not the actual input lines. The clock type determines when the data is loaded into these buffers. A RDY clock loads the buffers on a busy-to-ready transition of PFLG. A BSY clock loads the buffers on a ready-to-busy transition of PFLG. The RD clock loads the buffers as it is reading them. The setting of the switches that control the clock selection is described in Chapter 1. Software can override the input clock source switch settings on the GPIO 650 see Chapters 3 and 5 for the registers to modify.
 
A BSY or RDY clock would normally be chosen for transfers that use handshaking. These sources allow the user to know exactly when the data is going to be stored in the input buffers.
 
If the buffers are read without handshaking the RD clock source would normally be used. With the RD clock source the data read would be whatever is on the input lines when the computer reads the input buffers. If the clock source is BSY or RDY and PFLG is not toggled the buffer reads would always return the same value regardless of the input lines because the buffers would never be loaded with new data.
 
Handshaking Steps
A complete handshake involves five separate operations that take place in the order listed. The first two are optional depending on the configuration of the board.
 
1. A peripheral OK check can be made before the start of a transfer. The peripheral check consists of the computer reading the PSTS line, if it is a logical 1 the peripheral is considered OK.
 
2. A peripheral ready check can be made before proceeding with the transfer of each word of data. In this case the state of the PFLG line is checked. If PFLG is in the ready state the computer proceeds, if not, the computer waits until the peripheral puts PFLG in the ready state. The PFLG line is checked if Full-Mode handshakes are selected, it is not for Pulse-Mode handshakes.
 
3. The computer initiates the transfer by setting the PCTL and IO lines. The IO line indicates the direction of transfer while PCTL indicates the start of a handshake.
 
4. The peripheral reads the data output lines or writes information to the data input lines.
 
5. The peripheral acknowledges that it has read or written the data. It does this by setting or clearing the PFLG line.
 
Timing Diagrams
In the following pages the possible configurations for the Full and Pulse Mode input and output handshakes are illustrated and described. Since the IO line is always set high for a read and low for a write it will not be shown. The peripheral OK check will not be illustrated.
 
Full-Mode OUTPUT Handshakes
 
t0 - The computer waits until PCTL is clear and PFLG is ready before starting the transfer.
t1 - The computer puts the data on the output lines and sets the IO line low.
t2 - After the PCTL delay time has expired, PCTL is set. This indicates to the peripheral that there is valid data.
t3 - The peripheral sets PFLG to busy.
t4 - The ready to busy transition on PFLG clears the PCTL line.
t5 - The peripheral sets PFLG to ready.
 
Because the interface is set to full-mode the peripheral can read the data at any time from the falling edge of PCTL until the busy-to-ready transition of PFLG. The data stays valid since the interface will not change the output data until the interface returns to the ready condition of PCTL clear and PFLG ready.
 
Full-Mode ENTER Handshake, BSY Clock Source
 
t0 - The computer checks to see if the peripheral is ready. Since PCTL is clear and PFLG is ready the transfer can proceed.
t1 - The computer sets PCTL to start the transfer. The IO line is simultaneously set high.
t2 - The peripheral places the data on the input lines.
t3 - After the data lines have had time to settle the peripheral sets PFLG. The setting of PFLG clocks the data into the input buffers on the GPIO board.
t4 - The PCTL line is cleared automatically after PFLG goes busy.
t5 - The peripheral sets PFLG ready. Once PFLG is ready the peripheral is ready to start a new transfer.
 
Full-Mode ENTER Handshake, RDY Clock Source
 
t0 - The computer checks to see if the peripheral is ready. Since PCTL is clear and PFLG is ready the transfer can proceed.
t1 - The computer sets PCTL to start the transfer. The IO line is simultaneously set high if it was not already high.
t2 - The peripheral sets PFLG busy.
t3 - PCTL is cleared in response to PFLG being set to busy.
t4 - The peripheral puts the data on the input lines. This can be done simultaneously with PFLG being set to busy.
t5 - The peripheral sets PFLG ready after the data lines have had time to settle. The transaction of PFLG from busy to ready will clock the data into the buffers on the GPIO board. This also puts the interface in the ready state to start a new transfer.
 
Busy Pulses, Pulse-Mode OUTPUT Handshakes
 
With the interface set to pulse-mode transfers, the computer will initiate the transfer if PCTL is clear regardless of the state of PFLG.
t1 - The computer puts the data on the data out lines and sets the IO line low.
t2 - After the PCTL delay time has expired, the PCTL line is set. This indicates that the data is valid.
t3 - The peripheral reads the data then acknowledges the transfer by setting PFLG to busy.
t4 - The PCTL line is cleared by the PFLG ready-to-busy transition. Once PCTL is clear the computer is ready to start a new transfer.
t5 - It is not important when PFLG goes ready since the computer will start a new transfer even if it is busy.
 
Ready Pulses, Pulse-Mode OUTPUT Handshakes
 
The computer will initiate the transfer if PCTL is clear regardless of the state of PFLG.
t1 - The computer puts the data on the output lines and sets the IO line low.
t2 - After the PCTL delay time has expired, the PCTL line is set. This indicates the presence of valid data on the output data lines.
t3 - The peripheral puts PFLG in the ready state.
t4 - The peripheral completes the handshake by setting PFLG busy. This ready-to-busy transition clears the PCTL line. The peripheral should read the data before the PFLG ready-to-busy transition.
t5 - Once PCTL is clear the computer is ready to start a new transfer.
 
Busy Pulses, Pulse-Mode ENTER (BSY Clock Source)
 
The computer will initiate the transfer if PCTL is clear regardless of the state of PFLG.
t1 - The computer sets PCTL and the IO line is set high.
t2 - The peripheral writes the data onto the data input lines.
t3 - After a data settling time the peripheral sets PFLG to busy. This clocks the data into the GPIO board buffers.
t4 - The PCTL line goes clear due to the ready-to-busy transition.
t5 - Some time later the PFLG line returns to ready. The next transfer start will not wait for this action.
 
Busy Pulses, Pulse-Mode ENTER (RDY Clock Source)
 
The computer will initiate the transfer if PCTL is clear regardless of the state of PFLG.
t1 - The computer sets PCTL and the IO line is set high.
t2 - The peripheral writes the data onto the data input lines.
t3 - The peripheral sets PFLG to busy.
t4 - The PCTL line goes clear due to the PFLG ready-to-busy transition. At this point the computer considers the transaction complete and might read the buffers even though the data has not yet been clocked in.
t5 - The PFLG line returns to ready clocking the data into the GPIO board buffers.
Note: DO NOT USE THIS TRANSFER MODE. There is no way to guarantee that the peripheral can clock the data into the input data buffers before the computer reads the buffers. When the input data buffers are clocked late the data read will be from the previous handshake.
 
Ready Pulses, Pulse-Mode ENTER (BSY Clock Source)
 
The computer will initiate the transfer if PCTL is clear regardless of the state of PFLG.
t1 - The computer sets PCTL and the IO line is set high.
t2 - The peripheral sets PFLG to ready.
t3 - The peripheral writes its data to the input lines.
t4 - After the data has had time to settle the peripheral sets the PFLG line to busy. This transaction will clock the data into the input buffers on the GPIO board.
t5 - In response to the ready-to-busy transition on the PFLG line, PCTL is cleared and the interface is ready to initiate another transfer.
 
Ready Pulses, Pulse-Mode ENTER (RDY Clock Source)
 
The computer will initiate the transfer if PCTL is clear regardless of the state of PFLG.
t1 - The computer sets PCTL and the IO line is set high.
t2 - The peripheral writes the data to the input lines.
t3 - After the data has had time to settle the peripheral sets the PFLG line to ready. This transaction will clock the data into the input buffers on the GPIO board.
t4 - The peripheral will later set PFLG to busy.
t5 - In response to the ready-to-busy transition on the PFLG line, PCTL is cleared and the interface is ready to initiate another transfer.
 
General Purpose IO Lines
These lines are not used for handshaking and are available as aids in working with the peripheral. The usual purpose of each line is described.
 
PSTS Line
This is the peripheral status line. It can be used to check that the peripheral is still active or at least that the cable is still connected. The typical use is to have the peripheral pull the PSTS line to ground. The PSTS polarity is set so that low represents peripheral OK. If the cable becomes disconnected the line floats high due to the on-board pull-up resistors which causes the PSTS line to report that the peripheral is not OK.
 
PRESET Line
This is the peripheral reset line. When the board is reset this line pulses low for at least 15μs. This allows both the GPIO 650 and the peripheral to be reset at the same time. A reset is generally performed every time a new program that uses the board is run.
 
EIR line
This is the external interrupt request line. The board can be configured in software to cause an interrupt whenever this line is low. This lets the peripheral tell the computer when it needs attention. If not used as an interrupt source the EIR line can be used as a general-purpose input.
 
CTL0 and CLT1 Lines
These are the control 0 and control 1 lines. They have no predefined purpose but can be set and cleared from software as desired.
 
STI0 and STI1 Lines
These are the status 0 and status 1 lines. They have no predefined purpose but can be read from software as desired.
 
Interrupts
Interrupts are used to interrupt the computations that the computer is performing so that some other action can take place. The typical action with the GPIO 650 is the start or continuation of the transfer of data. Each interrupt source is enabled and disabled from software.
 
Interrupt Sources
Interface Ready
External Interrupt Request (EIR)
DMA Terminal Count (GPIO 650 only)
 
Interface Ready
This interrupt source becomes active whenever the interface is ready to start a new handshake. The interface is ready if PCTL is clear with pulse mode handshake or when PCTL is clear and PFLG is ready with full mode handshake.
 
Software drivers may use this interrupt when controlling transfers. To avoid conflicting with the software drivers do not enable this source while the driver is performing a transfer.
 
External Interrupt Request
The EIR line is the source for this interrupt. When the EIR line is low and External Interrupt Request is enabled an interrupt is be generated. This is generally used by the peripheral to inform the computer that it needs attention.
 
This interrupt source is not used by the software drivers and may be active at any desired time without conflicting with the driver.
 
DMA Terminal Count
This interrupt source is used by the software driver to control DMA transfers on the GPIO 650. Since it is used exclusively with DMA, TransEra supplied software drivers do not make it available to the user. Information on this interrupt is in Chapter 5 Programming Guide for GPIO 650.
 
DMA Transfers
DMA stands for Direct Memory Access. DMA is not supported on the GPIO 600. These transfers use a DMA controller on the computer to move the data between the GPIO board and the computers memory without using the computers CPU. DMA transfers are not as subject to the variable delays that exist with Interrupt or Polled (CPU controlled) transfers.
Using DMA is generally the fastest way to perform large transfers of data. Small transfers may be faster with polled transfers because of the time it takes to configure the DMA controller. TransEra supplied software drivers selects the transfer mode that is expected to be the fastest.
 
When performing 8-bit transfers with the peripheral the GPIO 650 performs two handshakes and then transfers the data with a single 16-bit DMA transfer. This doubles the maximum transfer rate with 8-bit peripherals.
 
The memory structure of a PC and the limitations of the DMA controller, limits the amount of data that can be transferred with a single DMA controller configuration from 1 to 65536 words. Where in the range a specific transfer starts depends on the physical location in memory that the data is using. When the DMA controller reaches that configuration’s limit it needs to be reconfigured. While the DMA controller is being reconfigured transfers with the peripheral are paused. The user will generally not be able to predict when these pauses will take place.
 
With the exception of the pause mentioned above, the maximum time that the computer should take to get ready for the next handshake is 4μs. With polled and interrupt modes the time for the computer to get ready can vary greatly depending on the speed of the machine and the resources that are in use.
 
Reset
Before using the GPIO board it is recommended that the board be reset. This puts the board and interface into a known state before accessing the interface. When the board is reset a reset pulse of at least 15μs is put on the PRESET line to inform the peripheral that a reset has taken place.