Chapter 3 HTBasic Software Interface
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This section explains how to use the GPIO board with HTBasic and the HTBasic software driver. With the introduction of HTBasic 9.0, Both the GPIO 600 and 650 cards are fully supported under all operating systems supported by the 9.0 release.
The interface is designed to duplicate the operation of the HP GPIO 98622A as close as possible so that few if any software changes need to be made when using either the GPIO 600 or GPIO 650 boards with HTBasic in place of the HP GPIO 98622A with RMB. The differences between the two systems are summarized in the section Differences Between TransEra and HP GPIO.
Differences Between TransEra and HP GPIO
This section gives the differences between the HP GPIO 98622A and the TransEra GPIO Boards.
Setup
TransEra 600 and 650: Board address must be set with dip switches for the PC.
HP: No address needs to be selected.
TransEra 600 and 650: ISC is set in software during the LOAD BIN command.
HP: ISC is selected with a dip switch.
TransEra 600 and 650: The interrupt is selected from software in the LOAD BIN command.
HP: An interrupt priority is selected with a dip switch.
TransEra 600: Identical to HP.
TransEra 650: The PCTL delay time is set from software.
HP: A resistor or capacitor is added to change the PCTL delay time.
TransEra 600: Does not support DMA.
TransEra 650: The DMA channel is selected from software in the LOAD BIN command.
HP: The DMA channel is selected with a DIP switch.
Operation
TransEra: Unused bits in Status and Readio registers are set to zero.
HP: Unused bits in Status registers are set to zero while unused bits in Readio registers are generally set to one.
TransEra 600: Used a DOUT CLEAR jumper but the output lines are set low regardless of the selected polarity.
TransEra 650: When in the on position the DCLR switch causes the data output lines to be set to a logical zero.
HP: Uses the DOUT CLEAR jumper to perform the same function as the GPIO 650.
Registers
TransEra 600: Does not use bits 0-5 of the Interrupt and DMA Status register.
TransEra 650: Does not use bits 1-5 of the Interrupt and DMA Status register and bit 0 reports if DMA is active.
HP: The Interrupt and DMA Status register uses these bits differently.
TransEra 600: Same as HP.
TransEra 650: Defines an Input Clock Source register to override the switch selected input clock sources.
HP: Does not have this register.
Control Registers
This section lists the control registers and explains the purpose of the control bits. These registers should be used instead of writeio registers for board control. All registers are 8-bit unless otherwise noted.
The value associated with each bit is the decimal representation of that bit being set.
Control Registers
Register Name
0 Interface Reset
1 Set PCTL
2 Peripheral Control
3 Data Out (16-bits)
4 Input Clock Source (GPIO 650 only)
- Interrupt Enable
Reset Interface
CONTROL Register 0
Writing a non-zero value to this register resets the interface.
Set PCTL
CONTROL Register 1
Writing a non-zero value to this register sets PCTL.
Peripheral Control
CONTROL Register 2
Bit 7
Value=128
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Bit 6
Value = 64
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Bit 5
Value = 32
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Bit 4
Value = 16
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Bit 3
Value = 8
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Bit 2
Value = 4
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Bit 1
Value = 2
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Bit 0
Value = 1
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0
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Report PSTS Error
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Set CTL1 Low
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Set CTL0 Low
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Bit 0: Set CTL0 Low
When this bit is set the CTL0 line is driven low. When clear, the CTL0 output is in a high impedance state.
Bit 1: Set CTL1 Low
When this bit is set the CTL1 line is driven low. When clear the CTL1 output is in a high impedance state.
Bit 2: Report PSTS Error
When set the interface will check the PSTS line before that start of each transfer. When clear the status of the PSTS line is ignored.
Data Out (16 bits)
CONTROL Register 3
Bit 15
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Bit 14
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Bit 13
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Bit 12
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Bit 11
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Bit 10
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Bit 9
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Bit 8
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DO15
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DO14
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DO13
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DO12
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DO11
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DO10
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DO9
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DO8
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Bit 7
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Bit 6
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Bit 5
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Bit 4
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Bit 3
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Bit 2
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Bit 1
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Bit 0
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DO7
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DO6
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DO5
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DO4
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DO3
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DO2
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DO1
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DO0
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This is the output data buffer. Each bit is output on the corresponding output line. The logic polarity is user selectable with switch 1.
Interface Parameters
Control Register 4 (not present on GPIO 600 or HP 98622A)
Bit 7
Value=128
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Bit 6
Value = 64
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Bit 5
Value = 32
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Bit 4
Value = 16
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Bit 3
Value = 8
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Bit 2
Value = 4
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Bit 1
Value = 2
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Bit 0
Value = 1
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0
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Clock Source
High Byte
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Clock Source
Low Byte
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Bits 0,1: Clock Source Low Byte
These bits select the input clock source for the low byte data buffer. These bits are cleared on LOAD BIN or reset. When clear, the switch 2 setting are used.
Bits 1-0 Clock Source
00 Switch Setting
01 RDY
10 BSY
11 RD
Bits 2,3: Clock Source High Byte
These bits select the input clock source for the high byte data buffer. These bits are cleared on LOAD BIN or reset. When clear, the switch 2 setting are used.
Bits 3-2 Clock Source
00 Switch Setting
01 RDY
10 BSY
11 RD
Interrupt Enable
Interrupt Enable Register
Bit 7
Value=128
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Bit 6
Value = 64
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Bit 5
Value = 32
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Bit 4
Value = 16
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Bit 3
Value = 8
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Bit 2
Value = 4
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Bit 1
Value = 2
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Bit 0
Value = 1
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0
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Enable
Interface
Ready
Interrupts
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Enable
EIR
Interrupts
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Bit 0: Enable Interface Ready Interrupts
When set, an interrupt is requested when the interface is ready. When clear, this interrupt source is disabled.
Bit 1: Enable EIR Interrupts
When set, an interrupt is requested when the EIR line is low. When clear, this interrupt source is disabled.
Status Registers
This section lists the status registers and explains what each bit returns. These registers should be used instead of readio registers for board control. All registers are 8-bit unless otherwise noted.
Status Registers
Register Name
0 Card Identification
1 Interrupt and DMA Status
2 Board Status
3 Data In (16-bit)
4 Interface Ready
5 Peripheral Status
Card Identification
STATUS Register 0
Reading this register returns the ID number of the GPIO driver. The ID number for the GPIO driver is 3.
Interrupt and DMA Status
STATUS Register 1
Bit 7
Value=128
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Bit 6
Value = 64
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Bit 5
Value = 32
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Bit 4
Value = 16
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Bit 3
Value = 8
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Bit 2
Value = 4
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Bit 1
Value = 2
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Bit 0
Value = 1
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Interrupts
Are
Enabled
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Interrupt is Requested
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Undefined
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DMA is Active
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Bit 0: DMA is Active
A DMA transfer is being performed. If clear DMA is not active. This bit is undefined on the GPIO 600.
Bit 6: Interrupt is Requested
If set an interrupt is currently requested. If clear no interrupts are requested.
Bit 7: Interrupts are Enabled
If set at least one interrupt source is enabled. If clear no interrupt sources are enabled.
Transfer Status
STATUS Register 2
Bit 7
Value=128
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Bit 6
Value = 64
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Bit 5
Value = 32
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Bit 4
Value = 16
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Bit 3
Value = 8
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Bit 2
Value = 4
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Bit 1
Value = 2
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Bit 0
Value = 1
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Undefined
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Handshake In
Progress
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Interrupts
Are
Enabled
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Transfer
In
Progress
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Bit 0: Transfer in Progress
If set a transfer is taking place. If clear a transfer is not active.
Bit 1: Interrupts are Enabled
This is the same as bit 7 of the Interrupt and DMA Status register. If set at least one interrupt source is enabled. If clear no interrupt sources are enabled.
Bit 2: Handshake in Process
If set a handshake is in progress. With pulse mode handshakes that means that PCTL is set. With full mode handshakes PTCL is set or PFLG is busy. If clear a handshake is not taking place.
Data In (16 bits)
STATUS Register 3
Bit 15
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Bit 14
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Bit 13
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Bit 12
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Bit 11
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Bit 10
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Bit 9
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Bit 8
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DI15
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DI14
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DI13
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DI12
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DI11
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DI10
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DI9
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DI8
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Bit 7
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Bit 6
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Bit 5
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Bit 4
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Bit 3
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Bit 2
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Bit 1
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Bit 0
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DI7
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DI6
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DI5
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DI4
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DI3
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DI2
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DI1
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DI0
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This register returns the value stored in the input buffers. The input buffers are updated according to the input clock source selected for each byte.
Interface Ready
STATUS Register 4
If set the interface is ready for a subsequent data transfer. If clear the interface is busy.
Peripheral Status
STATUS Register 5
Bit 7
Value=128
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Bit 6
Value = 64
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Bit 5
Value = 32
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Bit 4
Value = 16
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Bit 3
Value = 8
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Bit 2
Value = 4
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Bit 1
Value = 2
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Bit 0
Value = 1
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Undefined
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PSTS
OK
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EIR
Line Low
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STI1
Line Low
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STI0
Line Low
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Bit 0: STI0 Line Low
If set the STI0 line is low. If clear the line is high.
Bit 1: STI1 Line Low
If set the STI1 line is low. If clear the line is high.
Bit 2: EIR Line Low
If set the EIR line is low. If clear the EIR line is high.
Bit 3: PSTS OK
If set the PSTS line is OK. The polarity of the PSTS line is user selectable with switch 1. If clear the PSTS line is not OK.
Configuring and Loading
The Device Setup dialog is used for configuration and loading both cards. Once a driver is configured it may be loaded using the Device Setup, or by including a line like the following in your AUTOST file:
Model 600 Board
LOAD BIN "GPIO600[;ISC Isc][BASE Address][INTERRUPT Int]"
Model 650 Board
LOAD BIN "GPIO650[;ISC Isc][BASE Address][INTERRUPT Int] [DELAY Delay]"
Options
The legal options for the GPIO drivers are:
BASE AddressINTERRUPT InterruptISC IscDELAY Delay (650 only)
Once the driver is configured, it may be necessary to reboot the machine. Both the Device Setup Dialog and the LOAD BIN command load the software driver that HTBasic uses to communicate with the GPIO board. The LOAD BIN command must be executed before any access to the board from HTBasic.
For the DOS version, the driver filenames that the LOAD BIN uses for the GPIO 600 are ‘gpio.d86’ for the PC version and ‘gpio.d36’ for the 386 version. For the GPIO 650 the filenames are ‘gpio16.d86’ for the PC version and ‘gpio16.d36’ for the 386 version. Note: there is no Device Setup necessary in the DOS version.
If the default value is used that parameter does not need to be specified in the LOAD BIN command.
Parameter
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Default Value
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Range
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BASE
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380 (hex)
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200-3F0 (hex)
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ISC
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12
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4-32
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INT (GPIO 600)
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5
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0,2,3,4,5,6,7
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INT (GPIO 650)
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10
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0,5,7,9,10,11,12,15
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DMA (GPIO 650)
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6
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0,5,6,7
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DELAY (GPIO 650)
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1
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0-7
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The address set with the IO Address switch must match the BASE address value used for LOAD BIN. If these do not agree the LOAD BIN will give a device not found error.
The default ISC for the GPIO board is 12. This is the same ISC number assigned to the second parallel port. If the computer has a second parallel port the ISC of the GPIO board should be changed.
Interrupts may be disabled by using a 0 as the interrupt value. If interrupts are disabled the board will not support TRANSFER commands and ENTER and OUTPUT commands could be slower.
DMA transfers are only supported on the GPIO 650 under DOS. An interrupt channel must be specified for DMA to be used. DMA is not supported on the GPIO 600.
The DELAY option controls the PCTL delay time for the GPIO 650. This delay is the time from when the computer outputs the data onto the GPIO cable until the PCTL line is set. If set to a time shorter than the data settling time there can be data errors on outputs. A resistor or capacitor is added to the board to change the PCTL delay time for the GPIO 600.
Value
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Delay Time
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0
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0-100ns
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1
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200-300ns
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2
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400-500ns
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3
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600-700ns
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4
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800-9 00ns
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5
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1.0-1.1μs
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6
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1.2-1.3μs
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7
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1.4-1.5 μs
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An example LOAD BIN for the GPIO 650 with a base address of 220 hex, ISC number of 13, using interrupt channel 15 and with a PCTL delay of 400-500ns.
LOAD BIN "GPIO650; BASE 220 ISC 13 INT 15 DELAY 2"
The LOAD BIN for the GPIO 600 would be the same except the DMA and DELAY parameters would be left off and the INT parameter must match the jumper location.
Interface Reset
The interface should be reset before use to put the interface into a known state. It is reset when the CLR I/O or BASIC RESET key is pressed and when the LOAD BIN command is executed. The interface can be also be reset in software by writing a one to Reset Interface (control register 0).
The following occurs during a reset:
• The Peripheral Reset line (PRESET) is pulsed low for at least 15μs.
• The PCTL line is cleared.
• The interrupt enable bit is cleared. This disables interrupts until re-enabled.
• If the DCLR switch is set, the Data Out lines are set to a logic low on the GPIO 650. If the DOUT CLEAR jumper is set on the GPIO 600 the Data Out lines are set low.
• For the GPIO 650, the clock source high and low bits of Interface Parameters (control register 4) are set to 0. This forces the clock source to the switch two settings.
The following lines are unchanged by a reset:
• The CTL0 and CTL1 output lines.
• The IO line.
• The Data Out lines (if DCLR or DOUT CLEAR JUMPER is not set).
Using STATUS and CONTROL Commands for I/O
Reading status register three returns the value of the data buffers in 16-bit 2’s complement (-32768 to 32767). The value of these buffers depends on the clock source selected. With the RD source the buffers will be clocked just before reading so that the value read reflects the value on the input data lines. If RDY or BSY source is selected the value will be whatever was present during the previous handshake. The IO line is set high to indicate that a read is taking place. The status command does not use handshaking, therefore, it will not set PCTL to initiate a handshake.
STATUS Example
DI15-DI8 DI7-DI0
Gpio=12
STATUS Gpio,3;A 2 3
STATUS Gpio,3;B 255 255
With the RD clock source A = 515 (i.e.,256×2 +3) and B = -1.
Writing to control register three sets the data lines to the indicated value. The value is represented in 16-bit 2’s complement (-32768 to 32767). The IO line will be set low to indicate that an output was performed. No handshaking takes place since PCTL will not be set.
CONTROL Example
DO15-DO8 DO7-DO0
Gpio=12
CONTROL Gpio,3;5*256+11 5 11
CONTROL Gpio,3;-2 255 254
Status and Control registers can be used to control user defined handshaking. The following example demonstrates the use of the STATUS and CONTROL statements to perform handshaking with the CTL0, STI0, and IO lines. STI0 will not be able to clock the data into the input buffers since only PFLG is connected to the clocks but it can be used to indicate when there is valid data on the lines to be read. The RD clock source is required so that a status read will clock the data line values into the buffers before reading them.
User Handshake Example
Gpio=12
Num_samples=10
DIM Samples(10)
STATUS Gpio,3;Tmp ! Perform a dummy read to set IO high
FOR I=1 TO 10 ! This reads 10 data points
CONTROL Gpio,2;1 ! Set CTL0 to request communication
Loop1: Status GPIO,5;Stat5 ! Wait until peripheral sets STI0
IF NOT BIT(Stat5,0) THEN GOTO Loop1
STATUS Gpio,3;Samples(I) ! Read data point
CONTROL Gpio,2;0 ! Clear CTL0 to indicate data has been read
Loop2: STATUS Gpio,5;Stat5 ! Wait for STI0 to be cleared
IF BIT(Stat5,0) THEN GOTO Loop2 ! For a full handshake
NEXT I
Using OUTPUT and ENTER
Whenever the OUTPUT or ENTER command is used a complete handshake is required. If the handshake does not occur HTBasic gives one of following two responses: 1) If a timeout is set the interface will wait the allotted time then give a timeout error. 2) If the timeout period is not set the computer will appear to have locked up. Pressing the CLR I/O key restores control to the user. The default for the GPIO board is to not have the timeout set.
Most of the examples are of OUTPUT statements. ENTER statements require the same data on the same data lines that the OUTPUT statements produce.
The GPIO interface defaults to an 8-bit transfer unless otherwise specified.
The ASCII representations for A, B, and C are 65, 66, and 67 respectively. Carriage Return is 13 and Line Feed is 10. All values shown are in decimal.
OUTPUT String Example
DO15-DO8 DO7-DO0
Gpio=12
OUTPUT Gpio;"AB" 0 65
0 66
0 13
0 10
Only the low 8 bits are used for default transfers, Carriage Return Line Feed is the default delimiter.
OUTPUT Multiple Strings Example
DO15-DO8 DO7-DO0
Gpio=12
OUTPUT Gpio;"AB";"C" 0 65
0 66
0 67
0 13
0 10
Multiple strings are combined before outputting.
OUTPUT Word Default Delimiter
DO15-DO8 DO7-DO0
Gpio=12
OUTPUT Gpio USING "W";5*256+15 5 15
0 13
0 10
The default delimiter (byte mode) is still in effect.
OUTPUT Word No Delimiter
DO15-DO8 DO7-DO0
Gpio=12
OUTPUT Gpio USING "W,#";5*256+15 5 15
OUTPUT Gpio USING "W,#";-1 255 255
Numbers are output in 2’s complement 16-bit integers (-32768 to 32767).
OUTPUT Strings With Word Example
DO15-DO8 DO7-DO0
ASSIGN @Gpio TO 12;WORD,FORMAT ON
OUTPUT @Gpio;"A";"BC" 65 66
67 13
10 0
This transfer method would normally not be used due to the difficulty of having the peripheral reorganize the data.
OUTPUT Word Format Off Example
DO15-DO8 DO7-DO0
ASSIGN @Gpio TO 12;WORD,FORMAT OFF
OUTPUT @Gpio;5*256+11 5 11
OUTPUT @Gpio;-2 255 254
WORD,FORMAT OFF is equivalent to "W,#". This will execute the transfer of data 5-10 times faster than if the USING "W,#" were used.
OUTPUT Array Example
DO15-DO8 DO7-DO0
INTEGER I(10)
MAT I=(3*256+7)
ASSIGN @Gpio TO 12;WORD,FORMAT OFF
OUTPUT @Gpio;I(*) 3 7
3 7
ETC.
Arrays can be output with a single statement. By default HTBasic arrays are 0 based. This causes the above example to output 11 I(0)-I(10) words of data.
ENTER statements expect the same data, on the same numbered data input lines that a corresponding output statement produces.
ENTER Array Example
DI15-DI8 DI7-DI0
INTEGER I(10)
ASSIGN @Gpio TO 12;WORD,FORMAT OFF
ENTER @Gpio;I(*) 3 7
3 7
ETC.
Eleven handshakes complete the above transfer since INTEGER I(10) creates an array with eleven elements After the transfer, all entries of array "i" will contain 775 (i.e.,3X256 + 7).
Using the TRANSFER Command
The TRANSFER command allows data to be exchanged (similar to INPUT and OUTPUT commands) with the GPIO through I/O paths. The main difference between TRANSFER and INPUT/OUTPUT statements is TRANSFER can allow other HTBasic commands to be executed as it is executing. A TRANSFER can be thought of as a "background" process. A complete handshake is required when using TRANSFER. A timeout will only occur if the WAIT parameter is specified in the TRANSFER statement.
The following program reads 8 bytes using the TRANSFER statement at line 90. Every 4 bytes read will cause the subroutine at line 170 to be executed. After 2 records are read the transfer will be terminated and the subroutine at line 190 will be executed. Notice that HTBasic continues to execute after the TRANSFER statement is started.
Input TRANSFER Example
Gpio=12
INTEGER Xx,I,Cnt,Done
DIM X$[8] BUFFER ! Create the buffer
ASSIGN @Buf TO BUFFER X$;FORMAT OFF
ASSIGN @Dev TO Gpio
Done=0
ON EOR @Dev GOSUB L170 ! Set up end of record gosub
ON EOT @Dev GOSUB L190 ! Set up end of transfer gosub
! Transfer 2 four byte records
TRANSFER @Dev TO @Buf;RECORDS 2,EOR (COUNT 4)
L100: IF Done=0 THEN L100
STATUS @Buf,4;Cnt ! Read number of bytes in buffer
FOR I=1 TO Cnt
ENTER @Buf USING "#,B";Xx ! Read data from the buffer
PRINT USING "#,K,B,K,/";"[",Xx,"]"
NEXT I
PAUSE
L170:PRINT "END OF RECORD"
RETURN
L190: PRINT "END OF TRANSFER"
Done=1
RETURN
END
The following program outputs 8 bytes (4 words) to the GPIO. The ON EOR statement at line 90 will cause the subroutine at line 160 to be executed every 4 bytes transferred. The ON EOT statement at line 100 causes the subroutine at line 180 when the transfer is done. The data will be output one word (16 bits) at a time (4 handshake transfers). The first transfer will output 49 ("1") on D0-D7 and 50 ("2") on D8-D15.
Output TRANSFER Example
Gpio=12
INTEGER Bytes,I,Done
DIM X$[8] BUFFER ! Create the buffer
Bytes=8
ASSIGN @Buf TO BUFFER X$;FORMAT OFF
ASSIGN @Dev TO Gpio;WORD
! Load the buffer with a string
OUTPUT @Buf USING "#,K";"12345678"
Done=0
ON EOR @Dev GOSUB L160 ! Set up the end of record gosub
ON EOT @Dev GOSUB L180 ! Set up the end of transfer gosub
PRINT "START TRANSFER"
! Transfer 2 four byte records
TRANSFER @Buf TO @Dev;EOR (COUNT 4)
WHILE Done=0
END WHILE
PAUSE
L160: PRINT "END OF RECORD"
RETURN
L180: PRINT "END OF TRANSFER"
Done=1
RETURN
END
Maximizing the Speed of I/O Transfers
For many users the transfer rate of the GPIO board is not relevant since they are passing relatively small amounts of data and the board is fast enough. In other cases transfer rate can be critical. This section lists some ideas to help increase the transfer rate. These techniques are not always applicable but when used can increase performance 2-10 times verses other methods that perform the same task.
Assign a DMA channel to the GPIO interface if using the GPIO 650. When the board is allowed to use DMA the transfer will be able to move data at a rate of 250K word/second. Although pauses will occur in the transfer every 64K words to reinitialize the DMA controller it is still the fastest way to transfer with most machines. Note that timeouts are disabled during DMA transfers.
Avoid the use of USING statements with OUTPUT and ENTER commands. When USING is defined, HTBasic handles the transfer in a way that allows it to reformat the data if necessary. This occurs even if it does not reformat the data. This handling adds a large amount of overhead to the transfer. For an example, assigning FORMAT OFF, WORD to the GPIO device will execute outputs about 10 times faster than if USING "W,#" were specified in the OUTPUT statement. In both cases the output data will be the same.
The use of delimiting for ENTER and TRANSFER strings is usually required but the overhead of checking every byte to see if it is the delimiting character slows the transfer significantly. When the length of the data is known use COUNT with TRANSFERs. With ENTERs, ALLOCATE the array to the size of the data and then ENTER into that array.
HTBasic is very flexible when it comes to changing the type of data that is being used. This ability to change the data type can also result in significant overhead. When possible define arrays as integers and use the FORMAT OFF mode to transfer numeric data to the peripheral. If not specified the HTBasic default is FORMAT ON which converts the data into its ASCII representation before outputting it. This results in a large speed penalty.
These techniques are not limited to the exact situations described but the ideas of using DMA, not delimiting, using FORMAT OFF and avoiding data type changes can increase the data rate for many applications.
GPIO Timeouts
Timeouts are used to prevent the system from appearing to lock up when communication with the peripheral is not functioning.
The timeout period starts when PCTL is set and continues until the interface is ready. With a Pulse-Mode transfer it continues until PCTL is clear. For a Full-Mode transfer it continues until PCTL is clear and PFLG is ready.
When a timeout occurs the interface is reset. Refer to Interface Reset for a list of changes on reset. If the error is not trapped with an ON TIMEOUT instruction the program will terminate and display a timeout error.
When using DMA, timeouts are disabled. If the interface stops communicating during a transfer the computer can appear to lock up. Pressing the BASIC RESET key will terminate the program and return control to the user. If this is unacceptable DMA must be disabled by selecting DMA channel 0 when performing the LOAD BIN statement.
General Purpose Lines
There are four general-purpose lines that are available for any use. CTL1 and CTL0 are output lines and STI1 and STI0 are input lines. The lines are read and written to through status and control statements.
Peripheral Control
The CTLx lines are set by writing to Peripheral Control (control register 2). When writing to this register all the bits are modified. To avoid accidentally clearing other bits a software copy of the register should be kept. When a CTLx line it to be changed, bit modify the software copy and then write it to the control register. Note that CTLx has low-true polarity (1 = low). This polarity is not selectable.
CTLx Control Example
Gpio=12 ! 12 = Interface Select Code
Pcontrol=BINIOR(Pcontrol,1 ! Set CTL0
! Clear a bit by ANDing the register with the compliment
Pcontrol=BINAND(Pcontrol,BINCMP(2)) ! Clear CTL1
CONTROL Gpio,2;Pcontrol ! Write out value
This sets the CTL0 bit and clears the CTL1 bit in line 130. Since the outputs are inverted the CTL0 line is then forced low and the CTL1 line goes to high impedance.
The STIx lines are read by reading Peripheral Status (status register 5). The STIx lines have low-true polarity (1 = low). This polarity is not selectable.
Check STIx Status Example
Gpio=12 ! 12 = Interface Select Code
STATUS Gpio,5;Stat5 ! Read Peripheral Status
Sti0=BIT(Stat5,0) ! Check the STIx bits
Sti1=BIT(Stat5,1)
Using PSTS
The PSTS line is generally used to indicate if peripheral communication is operational. The interface can be enabled to check it before every OUTPUT, ENTER and TRANSFER command by setting the PSTS Error bit of the Peripheral Control Register. Its status can be read at any time, whether or not PSTS Checking is enabled, by reading the PSTS OK bit of Peripheral Status.
If the PSTS input is left floating (not connected to anything), it will read a high. Therefore it is recommended to set the polarity to low = OK. This way a disconnected cable will return a PSTS not OK signal.
Activate PSTS Checking Example
Gpio=12 ! 12 = Interface Select Code
Pcontrol=BINIOR(Pcontrol,4) ! Set PSTS Check
Deactivate PSTS Checking Example
Gpio=12
! Clear a bit by ANDing the register with the compliment
Pcontrol=BINAND(Pcontrol,BINCMP(4)) ! Clear CTL1
CONTROL Gpio,2;Pcontrol ! Write out value
Read PSTS Value Example
Gpio=12
STATUS Gpio,5;Pstatus ! Read Peripheral Status
Psts=BIT(Pstatus,2) ! Check Psts bit
HTBasic GPIO Interrupts
The GPIO interface supports Ready interrupts and External Interrupt Request (EIR) interrupts. Both of these interrupts are level-sensitive, this means that the signal must remain until it can be serviced. The service routine must be able to distinguish between the interrupts as they both call the same interrupt service routine.
Enabling Interrupts
After LOAD BIN or reset the interrupts are disabled. They are enabled by writing a new mask into the Interrupt Enable Register. The mask identifies which interrupts will be allowed to cause an interrupt. Set each desired interrupt bit to enable it.
Interrupt Mask Example
Gpio=12 ! 12 = Interface Select Code
ON INTR Gpio GOSUB Int
ENABLE INTR Gpio;1 ! Set the mask to 1 for EIR
Interface Ready
When the interface ready bit is set an interrupt occurs whenever the interface becomes ready. In Full-Mode Handshake the interface is ready whenever PCTL is clear and PFLG is ready. In Pulse-Mode Handshake the interface is ready when PCTL is clear regardless of the state of PFLG.
External Interrupt Request
When the EIR bit is set an interrupt occurs whenever the EIR line goes low. The polarity of this line cannot be changed. This line must be kept low until it is inside the service routine or it may be missed by the program.
Interrupt Service Routine
The interrupt service routine is the code that the computer executes if an interrupt occurs. A typical application is using an EIR interrupt to signal the computer that it has data available to be read. Interrupts are disabled after every call to the interrupt service routine. If the application requires multiple interrupts, the interrupts must be re-enabled during the interrupt service routine.
If both EIR and Interface Ready interrupts are enabled the service routine needs to be able to identify what caused the interrupt. This is accomplished by reading Interface Ready (status register 4) to see if the interface is ready or the EIR Line Low bit of Peripheral Status (status register 5) to check for an EIR interrupt.
The following example sets up an interrupt handler called Gpio_int to read one character each time EIR goes low. Eleven integer values will be read and then stored in the Samples array. In this example the peripheral needs to clear EIR when the sample point is read.
Interrupt Controlled Input
Gpio=12
Num_samples=10
Count=0
INTEGER Samples(10)
ON INTR Gpio GOSUB Gpio_int
ENABLE INTR Gpio;1 ! Enable the EIR interrupt
! The loop below can be replace by useful code while waiting
! for the transfer to be completed
Loop: DISP TIME$(TIMEDATE)
IF Count<Num_samples THEN GOTO Loop ! Wait for transfer
DISP "Transfer is complete"
STOP
Gpio_int: ! This is the interrupt handling routine
STATUS Gpio,5;Stat5
IF BIT(Stat5,2) THEN ! Check if a valid gpio interrupt exists
ENTER Gpio USING "W,#";Samples(Count)
Count=Count+1
ENABLE INTR Gpio ! Peripheral needs to clear EIR before
! this statement
END IF
RETURN
END
READIO and WRITEIO Registers
This section describes the GPIO Interface’s READIO and WRITEIO registers. These registers are made to be as compatible as possible with the registers from the HP GPIO 98622A. They are not the physical registers that exist on either of the the GPIO boards. To use these registers the driver must be loaded. The actual physical registers are listed in the Programming Guide sections of this manual.
In some cases both the HP and TransEra boards have similar bits but operation is different particularly with DMA operation. In these cases the control bits are left out of the READIO and WRITEIO registers.
READIO and WRITEIO registers should generally not be used. Most functions are available from STATUS and CONTROL register. Accessing WRITEIO registers can have undesirable effects by overriding settings that the software driver had set.
GPIO WRITEIO Registers
WRITEIO Register 0-Set PCTL
WRITEIO Register 1-Reset Interface
WRITEIO Register 2-Interrupt Mask
WRITEIO Register 3-Interrupt and DMA Enable
WRITEIO Register 4-MSB of Data Out
WRITEIO Register 5-LSB of Data Out
WRITEIO Register 6-Undefined
WRITEIO Register 7-Set Control Output Lines
Set PCTL
WRITEIO Register 0
Writing any non-zero numeric value to this register places PCTL in the Set state; writing zero causes no action.
Reset Interface
WRITEIO Register 1
Writing any non-zero numeric value to this register resets the interface.
Interrupt Mask
WRITEIO Register 2
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
0
|
Enable
Interface
Ready
Interrupts
|
Enable
EIR
Interrupts
|
Interrupt and DMA Enable
WRITEIO Register 3
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
Enable
Interrupts
|
0
|
MSB of Data Out
WRITEIO Register 4
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
DO15
|
DO14
|
DO13
|
DO12
|
DO11
|
DO10
|
DO9
|
DO8
|
LSB of Data Out
WRITEIO Register 5
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
DO7
|
DO6
|
DO5
|
DO4
|
DO3
|
DO2
|
DO1
|
DO0
|
Set Control Output Lines
WRITEIO Register 7
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
0
|
Set CTL1
(1= Low;
0= High)
|
Set CTL0
(1= Low;
0= High)
|
GPIO READIO Registers
Register 0-Interface Ready
Register 1-Card Identification
Register 2-Reserved
Register 3-Interrupt Status
Register 4-MSB of Data In
Register 5-LSB of Data In
Register 6-Reserved
Register 7-Peripheral Status
Interface Ready
READIO Register 0
A 1 indicates that the interface is Ready for subsequent data transfers, and 0 indicates Not Ready.
Board ID register
READIO Register 1
This register always contains 3, the identification for GPIO interfaces.
Interrupt Status
READIO Register 3
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
Interrupts
Are
Enabled
|
Interrupt is
Requested
|
Undefined
|
DMA
is Active
|
MSB of Data In
READIO Register 4
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
DI15
|
DI14
|
DI13
|
DI12
|
DI11
|
DI10
|
DI9
|
DI8
|
LSB of Data In
READIO Register 5
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
DI7
|
DI6
|
DI5
|
DI4
|
DI3
|
DI2
|
DI1
|
DI0
|
Peripheral Status
READIO Register 7
Bit 7
Value=128
|
Bit 6
Value = 64
|
Bit 5
Value = 32
|
Bit 4
Value = 16
|
Bit 3
Value = 8
|
Bit 2
Value = 4
|
Bit 1
Value = 2
|
Bit 0
Value = 1
|
Undefined
|
PSTS
OK
|
EIR
Line Low
|
STI1
Line Low
|
STI0
Line Low
|