This section provides the board level information necessary to write a device driver that can control the GPIO board without TransEra supplied software. This is difficult and not recommended for most users. If a driver is being used, writing to any of the hardware registers directly can cause undesirable results due to conflicts with the driver.
Throughout this section setting a bit refers to changing the bit to a logical one. Clearing a bit refers to changing the bit to a logical zero.
The control or status register number is the offset added to the base address. This gives the physical IO address required to access the board. The base address is selected with switch number one. The GPIO 600 has an 8-bit interface so it only uses 8-bit registers.
Hardware Register Description
A short explanation of the registers is given. Data is written to control register and read from status registers. The Control or Status register number is the offset from the base address of that register.
Register Summary
Control Registers
Status Registers
Set PCTL
Control Register 0
Writing any value to this register location causes PCTL to be set.
Reset Interface
Control Register 1
Writing any value to this register location resets the interface.
The following occurs during a reset:
• The PRESET line pulses low for at least 15ms.
• The PCTL line is cleared.
• The output data lines are cleared if the DOUT Clear jumper is intalled.
• Interrupts are disabled.
Interrupt Mask
Control Register 2
Bit 0: Enable EIR Interrupts
When set EIR interrupts are requested when the EIR line goes low as long as the Enable Interrupts bit (register 3 bit 3) is set. When clear EIR interrupts are disabled.
Bit 1: Enable Interface Ready Interrupts
When set an interrupt is generated whenever the board is ready and the Enable Interrupts bit (register 3 bit 3) is set.
Enable Interrupts
Control Register 3
Bit 3: Enable Interrupts
This it the board level enable interrupts. When set the interrupt mask determines which interrupts are valid. When clear all interrupts are disabled.
Set CTLx
Control Register 7
Bit 0: Set CTL0 Low
When set the CTL0 line is forced low. When clear the CTL0 line goes in a high impedance state.
Bit 1: Set CTL1 Low
When set the CTL1 line is forced low. When clear the CTL1 line goes in a high impedance state.
Low Data Out
Control Register 8
The data written to this register is output to the DO0-DO7 data lines (pins 17-10) and the IO line is forced low. The polarity of the data depends on the polarity selected by the DOUT switch.
High Data Out
Control Register 9
The data written to this register is output to the DO8-DO15 data lines (pins 9-2) and the IO line is forced low. The polarity of the data depends on the polarity selected by the DOUT switch.
High Data Out With PCTL
Control Register 10
The data written to this register is output to the DO8-DO15 data lines (pins 9-2) and the IO line is forced low. The polarity of the data depends on the polarity selected by the DOUT switch. Writing to this register instead of register 9 causes the PCTL line to be automatically set after the PCTL delay time. This is used to initiate output handshakes.
Interface Ready
Status register 0
Reading this register returns a 1 if the interface is ready. A 0 indicates that the interface is not ready. The conditions that result in interface ready are described in Chapter 2.
Board ID
Status register 1
This register always returns a 3. It is the board ID for the GPIO 600.
Interrupt Mask
Status register 2
This register always returns the interrupt mask. It is a copy of what was written to control register 2.
Interrupt Status
Status Register 3
Bit 2: Interrupt is Requested
When set an interrupt is currently requested by the GPIO board. When clear no interrupts are beign requested by the board.
Bit 3: Interrupts are Enabled
This returns the value written to the Enable Interrupt bit (register 3 bit 3).
Pperipheral Status
Status Register 7
Bit 0: STI0 is Low
When the STI0 line (pin 47) is low this bit is set to one. When the STI0 line is high it is clear.
Bit 1: STI1 is Low
When the STI1 line (pin 48) is low this bit is set to one. When the STI1 line is high it is clear
Bit 2: EIR is Low
If the EIR line (pin 46) is low this bit is set. When the EIR line is high it is clear.
Bit 3: PSTS is OK
This bit is set if the PSTS line (pin 45) is in the OK state. The polarity of OK is user selectable with switch 2.
Low Data In
Status Register 8
This register reads the low byte of the input data buffers. It also sets the IO line to a high impedance state.
High Data In
Status Register 9
This register reads the high byte of the input data buffers. It also sets the IO line to a high impedance state.
Start Read
Status Register 10
Reading this register sets the IO line to a high impedance state and sets PCTL to initiate an input read handshake.
IO Line Control
This section discusses the control or access of the IO lines.
CTL0
CTL0 is set or cleared by writing to the Set CTL0 bit (register 7 bit 0). When the CTL0 bit is set the line is driven low.
CTL1
CTL1 is set or cleared by writing to the Set CTL1 bit (register 7 bit 1). When the CTL1 bit is set the line is driven low.
EIR
The status of EIR is found by reading the EIR is Low bit (register 7 bit 3). When EIR is Low returns one the line is low.
IO
Conditions to set IO line
• Reading the Start Read register (register 10).
• Reading Low Data In (register 8) or High Data In (register 9) registers.
Conditions to clear IO line
• Writing to Low Data Out (register 8), High Data Out (register 9), or High Data Out With PCTL (register 10).
PCTL
Conditions to set the PCTL line
• Writing to Set PCTL (register 0).
• Starting a read cycle by reading Start Read (register 10).
• Writing to High Data Out With PCTL (register 10). This sets PCTL after the PCTL delay time.
Conditions to clear the PCTL line
• A ready-to-busy transition on PFLG.
• Writing to Reset Interface (register 1).
PRESET
The PRESET line is set low for at least 15μs by writing to Reset Interface (register 1).
PSTS
The PSTS line is checked by reading PSTS OK (register 7 bit 3). The polarity of the line is user selectable.
STI0
The status of STI0 is found by reading the STI0 is Low bit (register 7, bit 0). When set, the line is low.
STI1
The status of STI1 is found by reading the STI1 is Low bit (register 7, bit 1). When set, the line is low.
Interrupts
The two interrupt sources are controlled by the mask in Interrupt Mask and the global interrupt enable in Enable Interrupts. An interrupt source is selected when its corresponding bit is set in the Interrupt Mask. The selected source(s) can cause an interrupt when the Enable Interrupt bit of the Enable Interrupt register is set.
Which if any interrupt is active can be found by reading the Interrupt is Requested bit (register 3 bit 2). When both interrupts are enabled the source of the interrupt can be determined by checking the status of Interface Ready (register 0) and EIR is Low (register 7 bit 2).
Since the interrupt controller on an ISA bus is edge triggered the interrupt source must be cleared at some point in the interrupt handler before exiting. If it is never cleared the controller will not re-interrupt. This can be done by either clearing and then resetting the Enable Interrupts bit before exiting or reading Interrupt is Requested and looping back through the interrupt handler until it is clear.
Transferring Data
This section explains the steps required to transfer data between the board and peripheral. In all of the following transfer methods handshaking is required. If no handshaking is used, output and input single bytes or words using the Output Data and Input Data registers.
Input Transfer with Polling
This is the simplest input transfer method. It cannot be run as a background process.
Step 1. Set PCTL and force the IO line high by writing to the Start Read register.
Step 2. Repetitively check the Interface Ready register until it is set to one. This signals the end of the handshake.
Step 3. Read the input data. If an 8-bit transfer read the Low Data In only. For a 16-bit data transfer also read the High Data In register to get the high data byte.
Step 4. If more data is to be input return to step 1, otherwise, the transfer is completed.
Output Transfer with Polling
This is the simplest output transfer method. It cannot be run as a background process.
Step 1. Output the low byte of data to the Low Data Out register. If it is a 16-bit transfer output the high byte to the High Data Out With PCTL register. For an 8-bit transfer, output a 0 to the High Data Out With PCTL register. PCTL will be set automatically after the PCTL Delay time.
Step 2. Repetitively check the Ready Interface register until set to one. This signals the end of the handshake.
Step 3. If more data is to be output return to step 1, otherwise, the transfer is completed.
Interrupt Transfer
An interrupt transfer performs the same steps as a polled transfer with two key differences. During the transfer, instead of waiting for the Ready bit to go high the program can continue until a ready interrupt occurs. This lets the transfer proceed as a background process. The second difference is that the input and output of data and control of IO and PCTL is all done in the interrupt handler.
The ready interrupt is enabled by setting Enable Ready Interrupts (register 2 bit 1) and Enable Interrupts (register 3 bit 3). Clearing either bit disables ready interrupts. After the desired amount of data has been transferred the interrupt handler should disable ready interrupts as part of completing the transfer.
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||