Chapter 5 Programming Guide for GPIO 650

This section provides the board level information necessary to write a device driver that can control the GPIO board without TransEra supplied software. This is difficult and not recommended for most users. If a driver is being used, writing to any of the hardware registers directly can cause undesirable results due to conflicts with the driver.

Throughout this section setting a bit refers to changing the bit to a logical one. Clearing a bit refers to changing the bit to a logical zero.

The Action register (register 0) is so named because setting a bit causes an action to take place. When a one is written to a bit in this register the specified action takes place and the bit setting is discarded. Writing zeros to bit locations in the Action register has no effect. All other control registers are latched registers.

Every bit in a latched register assumes the written value. Keep a software copy of latched registers to prevent bits from being inadvertently cleared. The best way to modify a latched register is to change the software copy and then send the software copy to the board.

The GPIO board has a mix of 8 and 16 bit registers. For proper operation the data with the correct width must be sent to the registers. The registers that are indicated as 8 or 16 bits will correctly accept both data widths.

Hardware Register Description

A short explanation of the registers is given. Data is written to control register and read from status registers. The Control or Status register number is the offset from the base address of that register.

Register Summary

Control Registers

Offset	Name	Width
0	Action	8-bit
1	Board Control	8-bit
2	Board Setup	16-bit
4	Output Data	8/16-bit
5	Output High Data	8-bit
6	Handshake Data Output	16-bit

Status Registers

Offset	Name	Width
0	Board Status	16-bit
2	Board ID	8-bit
4	Input Data	8/16-bit
5	Input High Data	8-bit

Action

Control Register 0 (8-bit)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0				Clear TC	Start Read	Reset Peripheral	Set PCTL

Bit 0: Set PCTL

Writing 1 to this bit causes the PCTL line to be set. Writing 0 does nothing.

Bit 1: Reset Peripheral

Writing 1 to this bit causes the PRESET line to pulse low for about 15us. PCTL is also put in the cleared state. Writing 0 does nothing.

Bit 2: Start Read

Writing 1 to this bit causes the board to start a read handshake cycle. It sets IO high and sets PCTL. Writing 0 does nothing.

Bit 3: Clear TC

Writing 1 to this bit clears the terminal count latch for channel A. Writing 0 does nothing.

Board Control

Control Register 1 (8-bit)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Word Transfers	0	Enable DMA Outputs	Enable DMA Inputs	Enable Interrupts	Enable TC Interrupts	Enable Ready Interrupts	Enable EIR Interrupts

Bit 0: Enable EIR Interrupts

When set, and if interrupts are enabled, an interrupt will be requested when EIR is low. If clear, the EIR line cannot cause an interrupt.

Bit 1: Enable Ready Interrupts

When set, and if interrupts are enabled, an interrupt will be requested when the interface is ready. If clear, ready interrupts will not be generated.

Bit 2: Enable TC Interrupts

When set, and if interrupts are enabled, an interrupt will be requested when a DMA terminal count is latched by the board. If clear, latched terminal counts cannot cause an interrupt.

Bit 3: Enable Interrupts

This is the general board level interrupt enable bit. When set, any enabled interrupts can take place. When clear, no interrupts will be requested.

Bit 4: Enable DMA Inputs

When set, the board attempts to perform DMA input transfers. When clear input DMA transfers are disabled.

Bit 5: Enable DMA Outputs

When set, the board attempts to perform DMA output transfers. When clear output DMA transfers are disabled.

Bit 7: Word Transfers

This controls the data width for DMA transfers only. When set the board outputs 16-bit data to the peripheral during DMA transfers. When clear 8-bit data are used with the high byte forced to a logical zero.

Board Setup

Control Register 2

Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8
Clock high		Clock Low		PCTL Delay Time			0

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0	DMA Select		Interrupt Select			Ctl1 Line Low	CTL0 Line Low

Bit 0: CTL0 Line Low

When set, the CTL0 line (pin 22) is driven low. When clear, the CTL0 line output is set to a high impedance state.

Bit 1: Ctl1 Line Low

When set, the Ctl1 line (pin 23) is driven low. When clear, the Ctl1 line output is set to a high impedance state.

Bits 2-4: Interrupt Select

These bits select the physical PC interrupt that the board will use.

Bits 4-2	Interrupt
000	Disabled
001	IRQ5
010	IRQ7
011	IRQ9
100	IRQ10
101	IRQ11
110	IRQ12
111	IRQ15

Bits 5-6: DMA Select

These bits select the physical PC DMA channel that the boards DMA channel will use.

Bits 6-5	DMA Channel
00	Disabled
01	DMA5
10	DMA6
11	DMA7

Bits 9-11: PCTL Delay

These bits control the settling time for the output data. It is the time from the writing of the data using Handshake Data Output (register 6) until PCTL is set.

Bits 11-9	Delay Time
000	0-100ns
001	200-300ns
010	400-500ns
011	600-700ns
100	800-900ns
101	1.0-1.1μs
110	1.2-1.3μs
111	1.4-1.5μs

Bits 12-13: Clock Low

These bits select the clock source for the low data byte.

Bits 13-12	Clock Source
00	Switch Setting
01	RDY
10	BSY
11	RD

Bits 14-15: Clock High

These bits select the clock source for the high data byte.

Bits 15-14	Clock Source
00	Switch Setting
01	RDY
10	BSY
11	RD

Output Data

Control Register 4 (8/16-bits)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
DO7	DO6	DO5	DO4	DO3	DO2	DO1	DO0

An 8-bit write is output to the DO0-DO7 lines (pins 17-10). A 16-bit write controls both the Output Low Data Register and the Output High Data Register (register 5). The low byte is output to the DO0-DO7 lines while the high byte is output to the DO8-DO15 lines (pins 9-2).

Output High Data

Control Register 5 (8-bits)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
DO15	DO14	DO13	DO12	DO11	DO10	DO9	DO8

Writes to this register are output to the DO8-DO15 lines (pins 9-2). 16-bit writes to register 4 also control this register.

Handshake Data Output

Control Register 6 (16-bit)

Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8
DO15	DO14	DO13	DO12	DO11	DO10	DO9	DO8

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
DO7	DO6	DO5	DO4	DO3	DO2	DO1	DO0

Writes to this register are output to the DO0-DO15 lines (pins 17-2). PCTL is then set automatically after the PCTL delay time to start the handshake.

Board Status

Status Register 0 (16-bit)

Bit 15	Bit 14	Bit 13	Bit 12	Bit 11	Bit 10	Bit 9	Bit 8
Undefined	Word Transfers	Undefined		DMA Terminal Count	Undefined	Active DMA	Interrupt is Requested

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
TC Interrupt	EIR Interrupt	Ready Interrupt	PSTS OK	EIR is Low	STI1 is Low	STI0 is Low	Ready

Bit 0: Ready

If set, the interface is ready for an IO transfer. If clear, an IO transfer is in progress.

Bit 1: STI0 is Low

If set, the STI0 line (pin 47) is low. If clear, the STI0 line is high.

Bit 2: STI1 is Low

If set, the STI1 line (pin 48) is low. If clear, the STI1 line is high.

Bit 3: EIR is Low

If set, the EIR line (pin 46) is low. If clear, the EIR line is high.

Bit 4: PSTS OK

If set, the PSTS check reports OK. The actual line polarity is controlled by the PSTS switch. If clear, PSTS check is not OK.

Bit 5: Ready Interrupt

If set, a ready interrupt is requested. If clear, a ready interrupt is not requested.

Bit 6: EIR Interrupt

If set, an EIR interrupt is requested. If clear, an EIR interrupt is not requested.

Bit 7: TC Interrupt

If set, a DMA terminal count interrupt is requested. If clear, a DMA terminal count interrupt is not requested.

Bit 8: Interrupt is Requested

If set, an interrupt is requested. This is a logical OR of the three specific interrupt sources. If clear, no interrupt is requested.

Bit 9: Active DMA

If set, DMA is currently active. If clear, DMA is not active.

Bit 11: DMA Terminal Count

The DMA controller has sent a terminal count signal to the board while the board was performing a DMA transfer. This bit remains set until cleared by a Clear TC strobe (register 0 bit 3). If clear, a valid terminal count has not occurred.

Bit 14: Word Transfers

This returns the value of the Word Transfers bit (register 1, bit 7).

Board ID

Status Register 2 (8-bits)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0	1	1	0	0	0	1	1

This register returns the board ID number of 99 (63 hex).

Input Data

Status Register 4 (8/16-bits)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
DI7	DI6	DI5	DI4	DI3	DI2	DI1	DI0

An 8-bit read returns the value of the low byte of the input data buffer that is connected to DI0-DI7 lines (pins 42-35). A 16-bit read returns the value of input low data buffer as the least significant byte and the value of the input high buffer as the most significant byte.

Input High Data

Status Register 5 (8-bits)

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
DI15	DI14	DI13	DI12	DI11	DI10	DI9	DI8

Returns the value stored in the input high data buffer that is connected to pins DI8-DI15 (pins 34-17).

IO Line Control

This section discusses the control or access of the IO lines.

CTL0

CTL0 is set or cleared by writing to the Set CTL0 bit (register 2 bit 0). When the CTL0 bit is set the line is driven low.

CTL1

CTL1 is set or cleared by writing to the Set CTL1 bit (register 2 bit 1). When the CTL1 bit is set the line is driven low.

EIR

The status of EIR is found by reading the EIR is Low bit (register 0, bit 3). When EIR is Low returns one the line is low.

Conditions to set IO line

• Writing a one to Start Read (register 0 bit 2).

• Reading Input Data (register 4) or Input High Data (register 5) registers.

• Enabling an input DMA cycle by setting the Enable DMA Inputs bit

(register 1, bit 4).

Conditions to clear IO line

• Writing to Output Data (register 4), Output High Data (register 5), or Handshake Data Output (register 6).

• Enabling an output DMA cycle by setting the Enable DMA Outputs bit (register 1, bit 5).

PCTL

Conditions to set the PCTL line

• Writing a 1 to Set PCTL (register 0 bit 0).

• Starting a read cycle by writing a 1 to Start Read (register 0 bit 2).

• Writing to Handshake Data Output (register 6). This sets PCTL after the PCTL delay time.

Conditions to clear the PCTL line

• A ready-to-busy transition on PFLG.

• Writing a 1 to Reset Peripheral (register 0 bit 1).

PRESET

The PRESET line is set low for about 15us by writing a 1 to the Reset Peripheral bit (register 0, bit 1).

PSTS

The PSTS line is checked by reading PSTS OK (register 0 bit 4). The polarity of the line is user selectable.

STI0

The status of STI0 is found by reading the STI0 is Low bit (register 0, bit 1). When set, the line is low.

STI1

The status of STI1 is found by reading the STI1 is Low bit (register 0, bit 2). When set, the line is low.

Initializing the Board

Before using the board the input clock source, PCTL delay time, interrupt number, DMA channel(s) and transfer width should be selected.

Input Clock Source

The input clock source for the high and low byte is controlled by the Clock High and Clock Low bit fields (register 2 bits 12-15).

Bits 13-12	Clock Source
00	Switch Setting
01	RDY
10	BSY
11	RD

Bits 14-15: Clock High

These bits select the clock source for the high data byte.

Bits 15-14	Clock Source
00	Switch Setting
01	RDY
10	BSY
11	RD

PCTL Delay Time

The PCTL delay time is set with the PCTL Delay Time bit field (register 2, bits 8-10).

Bits 11-9	Delay Time
000	0-100ns
001	200-300ns
010	400-500ns
011	600-700ns
100	800-900ns
101	1.0-1.1us
110	1.2-1.3us
111	1.4-1.5us

Interrupt Number

The board’s interrupt number is selected using the Interrupt Select bit field (register 2 bits 2-4).

Bits 4-2	Interrupt
000	Disabled
001	IRQ5
010	IRQ7
011	IRQ9
100	IRQ10
101	IRQ11
110	IRQ12
111	IRQ15

DMA Channel

The DMA channels are selected with the DMA Channel bit field (register 2 bits 5-6).

Bits 6-5	DMA Channel
00	Disabled
01	DMA5
10	DMA6
11	DMA7

Interrupts

The three interrupt sources are controlled by four bits in the DMA and Interrupt Control register (register 1). Enable EIR Interrupts, Enable Ready Interrupts and Enable TC Interrupts enable each of these interrupt sources individually. They make up the interrupt mask. The Enable Interrupt bit is the global enable that must be set for any interrupt to be enabled.

Which if any interrupt is active can be found by reading Board Status (register 0). Interrupt is Requested (bit 8) indicates that at least one interrupt is active. TC Interrupt, EIR Interrupt and Ready Interrupt are set if that particular interrupt is active.

Since the interrupt controller on an ISA bus is edge triggered the interrupt source must be cleared at some point in the interrupt handler before exiting. If it is never cleared the controller will not re-interrupt. This can be done by either clearing and then resetting Enable Interrupts before exit or reading Interrupt is Requested and looping back through the interrupt handler until it is clear.

Transferring Data without DMA

This section explains the steps required to transfer data between the board and peripheral. In all of the following transfer methods handshaking is required. If no handshaking is used, output and input single bytes or words using the Output Data and Input Data registers.

The required board information for controlling transfers with the GPIO board is included. The information necessary to program the DMA controller, interrupt controller, and properly allocate memory is beyond the scope of this manual.

Input Transfer with Polling

This is the simplest input transfer method. It cannot be run as a background process.

Step 1. Set PCTL and force the IO line high by writing a one to Start Read (register 0 bit 2).

Step 2. Repetitively check Ready (register 0, bit 0) until set. This signals the end of the handshake.

Step 3. Read the input data. Use an 8-bit read of Input Data Register (register4) for byte transfers or a 16-bit read of the same register for word transfers.

Step 4. If more data is to be input return to step 1, otherwise, the transfer is completed.

Output Transfer with Polling

This is the simplest output transfer method. It cannot be run as a background process.

Step 1. Output the data, set PCTL and set IO low by performing a 16-bit write to the Handshake Data Output register (register 6). If performing a byte transfer the high byte should be set to zero.

Step 2. Repetitively check Ready (register 0, bit 0) until set. This signals the end of the handshake.

Step 3. If more data is to be output return to step 1, otherwise, the transfer is completed.

Interrupt Transfer

An interrupt transfer performs the same steps as a polled transfer with two key differences. During the transfer, instead of waiting for the Ready bit to go high the program can continue until a ready interrupt occurs. This lets the transfer proceed as a background process. The second difference is that the input and output of data and control of IO and PCTL is all done in the interrupt handler.

The ready interrupt is enabled by setting Enable Ready Interrupts (register 1 bit 1) and Enable Interrupts (register 1 bit 3). Clearing either bit disables ready interrupts. After the desired amount of data has been transferred the interrupt handler should disable ready interrupts as part of completing the transfer.

DMA Transfers

DMA transfers are performed by the DMA controller on the computer. This allows a background transfer that is faster and more deterministic than interrupt or polled transfers.

The DMA hardware on the board controls handshaking during the DMA cycles. The IO line is forced high when Enable DMA Inputs (register 1 bit 4) is set and low when Enable DMA Outputs (register 1 bit 5) is set. This will override any attempts to change the IO line setting by other software means. The PCTL line is set as needed to carry out the transfer.

All DMA transfers are 16-bit transfers. If the interface is set for 8-bit transfers the board hardware will perform two 8-bit handshakes for every 16-bit DMA transfer. In this mode the low byte is first in the 8-bit data stream. This allows the bytes to be stored in memory in the same order as the handshakes.

DMA Transfer Steps

If only one DMA controller configuration is required all references to interrupts may be ignored.

Step 1. Make sure that DMA is disabled by clearing Enable DMA Inputs (register 1 bit 4) and Enable DMA Outputs (register 1 bit 5). The interface should be set for the desired byte or word transfers with the Word Transfer bit (register 1 bit 7).

Step 2. Configure the DMA controller.

Step 3. Verify that no old terminal counts are latched by writing a one to Clear TC (register 0 bit 3).

Step 4. Start the DMA transfer and enable TC interrupts by setting Enable DMA Inputs (register 1 bit 4) for input transfers, Enable DMA Outputs (register 1 bit 5) for output transfers, Enable TC Interrupts(register 1 bit 2), and Enable Interrupts (register 1 bit 3).

The DMA controller will cause a TC interrupt each time the controller has completed the programmed transfer. The interrupt handler must then reset the DMA controller to transfer more data or clear the bits set in step 4 to end the transfer. The interrupt handler is discussed in the DMA Interrupt Handler section.

When terminating an input DMA handshake clear Enable DMA Input before clearing the TC latch. When input DMA is enabled the board automatically performs input handshakes until TC is latched. If cleared in the wrong order the board will attempt to perform one extra handshake in word mode and two extra in byte mode.

When inputting or outputting odd numbers of byte data the last byte cannot be output with DMA. Since each DMA transfer moves two bytes of data there is no way to prevent an extra handshake for the second not needed byte. To avoid this problem set up the DMA controller to stop before the last byte is output or entered. The last byte can then be easily handled by transferring it from the interrupt handler after DMA has been disabled.

When performing a DMA transfer an potential interrupt is generated each time the DMA controller has finished transferring the configured amount of data. By interrupting on this event the controller can be reconfigured to transfer more data or the board’s DMA control bits can be cleared to end the DMA transfer.

DMA Interrupt Handler

Step 1. Verify that it is a TC interrupt by checking to see if TC Interrupt (register 0 bit 7) is set. If it is not a TC interrupt take care of the interrupt source and leave the interrupt handler. If more data is to be transferred proceed to step 2 otherwise go to step 4.

Step 2. Reprogram the DMA controller to transfer from/to the next block of memory.

Step 3. Clear the terminal count by writing a one to Clear TC (register 0, bit 3). Goto step 5.

Step 4. Clear either Enable DMA Outputs (register 1 bit 5) or Enable DMA Inputs (register 1 bit 4), Enable TC Interrupts (register 1 bit 2) and, if no other interrupts are active, Enable Interrupts (register 1 bit 3).

Step 5. Check that no interrupts are requested by reading the Interrupt is Requested bit (register 0 bit 8). If an interrupt is still requested handle it before exiting.

Step 6. Reinitialize the interrupt controller.

Step 7. Exit the interrupt handler.