Interrupt Enable Register Bit Mask

Bit	Value	Meaning
15	-32768	Active Controller
14	16384	Parallel Poll Config. change
13	8192	My Talk address received
12	4096	My Listen address received
11	2048	EOI received
10	1024	SPAS
9	512	Remote/Local change
8	256	Talker/Listener Address change
7	128	Trigger received
6	64	Handshake Error
5	32	Unrecognized universal command
4	16	Secondary command while addressed
3	8	Clear received
2	4	Unrecognized addressed command
1	2	SRQ received
0	1	IFC received

The interrupt enable register has the same bit values as STATUS registers 4 and 5. STATUS register 4 tells which condition caused the interrupt. STATUS register 5 tells which interrupts are enabled. To enable more than one interrupt, add up all the event decimal values and use this value as the ENABLE INTR bit mask.