Interrupt Enable Mask. This register is set with the ENABLE INTR statement.
Note: It is recommended that bit 1, Interrupt if Tx Holding Reg. Empty, not be used because any time ENABLE INTR is executed, this register will be empty and the interrupt will immediately occur. The interrupt-driven receive buffer code will then immediately acknowledge the interrupt as a side effect of checking for data in the receiver.
|
Bit
|
Value
|
Meaning
|
|
7-4
|
-
|
Not used
|
|
3
|
8
|
Interrupt if Modem Status (register 11) changes
|
|
2
|
4
|
Interrupt on error (register 10, bits 1 to 4)
|
|
1
|
2
|
Interrupt if Transmit Holding Reg Empty
|
|
0
|
1
|
Interrupt if data becomes available
|